1. Field of the Invention
This invention relates to an apparatus for producing a multi-scene video signal consisting of a plurality of video signals having different synchronizations respectively so that a plurality of scenes provided by the respective video signals can be simultaneously displayed in one frame.
2. Description of the Related Art
The term "multi-scene video signal producing apparatus" used herein indicates such an apparatus which can produce a video signal for simultaneously displaying N.times.N scenes (where N is a factor splitting one frame in both the horizontal and vertical directions and is a positive integer larger than and including 2), or the term indicates such an apparatus which can produce a video signal for simultaneously displaying a plurality of scenes in a superposed relation in one frame. The basic principle of operation of the latter apparatus is the same as that of the former apparatus. Therefore, a multi-scene video signal producing apparatus in which the value of N is selected to be N=2 to produce a multi-scene video signal for simultaneously displaying four scenes when one frame is split into four regions will be described by way of example.
FIG. 6 shows schematically the structure of a prior art multi-scene video signal producing apparatus. Referring to FIG. 6, digital video input signals 50, 51, 52 and 53 applied with timing of respectively different phases or frequencies are connected to memories 54, 55, 56 and 57 storing data corresponding to 1/4 of one frame respectively. The video input signals 50 to 53 compressed in their scene sizes to 1/4 of one frame respectively are written in the memories 54 to 57 with their phases or frequencies synchronized with the input timing respectively. Then, with the read timing that does not coincide with the write timing, the memories 54 to 57 are changed over to read out the data composing one frame size, so that a multi-scene video signal including four scenes in one frame appears at an output terminal 58 of the apparatus. Thus, the write timing and the read timing for each of the memories 54 to 57 differ in the phase or frequency.
However, when a single memory having a capacity large enough for storing all of the four scenes is used in the prior art multi-scene video signal producing apparatus, the four video input signals must be written in the large capacity memory with a plurality of timings having different phases or frequencies respectively, and the stored data must then be read out from the memory with read timings different from the write timings respectively, resulting in complexity of the memory read/write access timing. After all, such a large capacity memory could not be used in the prior art apparatus.
According to another method proposed hitherto, four or more small capacity memories are used to provide four blocks similar to the aforementioned memories 54 to 57, and each video input signal is allotted to one block. However, the above proposal has been defective in that the memory costs inevitably increase, and the number of required parts also inevitably increases due to the fact that a large capacity memory having a low bit cost cannot be used. Also, in the case of displaying multiple scenes in one frame split into, for example, nine or sixteen regions, it is necessary to use at least nine or sixteen memories although their capacity is relatively small. The problems pointed out above are thus quite serious.